291 patents
Page 2 of 15
Utility
Method of Forming Memory Cells, High Voltage Devices and Logic Devices on a Semiconductor Substrate
14 Sep 23
A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.
Zhuoqiang Jia, Leo Xing, Xian Liu, Serguei Jourba, Nhan Do
Filed: 7 Jun 22
Utility
Precise programming method and apparatus for analog neural memory in an artificial neural network
12 Sep 23
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 23 Jan 20
Utility
Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate
22 Aug 23
A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.
Guo Xiang Song, Chunming Wang, Leo Xing, Xian Liu, Nhan Do
Filed: 4 Jun 21
Utility
Memory Device of Non-volatile Memory Cells
17 Aug 23
A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns.
Hieu Van Tran, NHAN DO, FARNOOD MERRIKH BAYAT, XINJIE GUO, DMITRI STRUKOV, VIPIN TIWARI, MARK REITEN
Filed: 28 Apr 23
Utility
Method of Forming a Semiconductor Device with Memory Cells, High Voltage Devices and Logic Devices on a Substrate Using a Dummy Area
17 Aug 23
A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material.
Zhuoqiang Jia, Leo Xing, Xian Liu, Serguei Jourba, Nhan Do
Filed: 16 May 22
Utility
Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network
15 Aug 23
Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 14 Dec 20
Utility
Programming analog neural memory cells in deep learning artificial neural network
15 Aug 23
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 2 May 22
Utility
Calibration of Electrical Parameters In a Deep Learning Artificial Neural Network
10 Aug 23
Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network.
Hieu Van Tran
Filed: 22 Apr 22
Utility
Method Of Scanning An Image Using Non-volatile Memory Array Neural Network Classifier
10 Aug 23
A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 24 Mar 23
Utility
Artificial Neural Network Comprising an Analog Array and a Digital Array
3 Aug 23
Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 14 Apr 22
Utility
Method of Forming Pairs of Three-gate Non-volatile Flash Memory Cells Using Two Polysilicon Deposition Steps
27 Jul 23
A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions.
Feng Zhou, XIAN LIU, CHIEN-SHENG SU, Nhan DO, CHUNMING WANG
Filed: 27 Mar 23
Utility
Summing Circuit for Neural Network
20 Jul 23
Numerous examples of summing circuits for a neural network are disclosed.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 20 Mar 23
Utility
Split Array Architecture for Analog Neural Memory In a Deep Learning Artificial Neural Network
20 Jul 23
Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 23 Mar 23
Utility
Output Circuitry for Non-volatile Memory Array In Neural Network
20 Jul 23
Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods.
Farnood Merrikh BAYAT, Xinjie GUO, Dmitri STRUKOV, Nhan DO, Hieu Van TRAN, Vipin TIWARI, Mark REITEN
Filed: 20 Mar 23
Utility
Neural Network Classifier Using Array of Three-gate Non-volatile Memory Cells
13 Jul 23
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 21 Mar 23
Utility
Verification of a Weight Stored In a Non-volatile Memory Cell In a Neural Network Following a Programming Operation
29 Jun 23
Numerous examples are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 10 Mar 23
Utility
Address Fault Detection In a Memory System
25 May 23
Various examples of memory systems comprising an address fault detection system are disclosed.
Hieu Van Tran
Filed: 28 Jan 22
Utility
Determination of a Bias Voltage to Apply to One or More Memory Cells In a Neural Network
18 May 23
Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed.
Hieu Van Tran
Filed: 26 Jan 22
Utility
Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps
16 May 23
A simplified method for forming a non-volatile memory cell using two polysilicon depositions.
Feng Zhou, Xian Liu, Chien-Sheng Su, Nhan Do, Chunming Wang
Filed: 15 Sep 20
Utility
Transceiver for Providing High Voltages for Erase or Program Operations In a Non-volatile Memory System
11 May 23
Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed.
Hieu Van Tran, Anh Ly, Kha Nguyen, Hien Pham, Duc Nguyen
Filed: 26 Jan 22