291 patents
Page 3 of 15
Utility
Neural network classifier using array of three-gate non-volatile memory cells
9 May 23
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 9 Sep 21
Utility
Set-while-verify circuit and reset-while verify circuit for resistive random access memory cells
9 May 23
Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed.
Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
Filed: 11 Mar 21
Utility
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25 Apr 23
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 25 Mar 20
Utility
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20 Apr 23
Examples of programming circuits and methods are provided.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 14 Dec 22
Utility
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11 Apr 23
The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM.
Guangming Lin, Xiaozhou Qian, Xiao Yan Pi, Vipin Tiwari, Zhenlin Ding
Filed: 7 Jan 22
Utility
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6 Apr 23
Examples of programming circuits and methods are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 13 Dec 22
Utility
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4 Apr 23
A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
Filed: 23 Mar 22
Utility
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30 Mar 23
A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1.
Yuri Tkachev, JINHO KIM, CYNTHIA FUNG, GILLES FESTES, BERNARD BERTELLO, PARVIZ GHAZAVI, BRUNO VILLARD, JEAN FRANCOIS THIERY, CATHERINE DECOBERT, SERGUEI JOURBA, FAN LUO, LATT TEE, NHAN DO
Filed: 14 Jan 22
Utility
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7 Mar 23
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Vipin Tiwari
Filed: 6 Aug 20
Utility
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28 Feb 23
A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 8 Apr 22
Utility
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23 Feb 23
Numerous embodiments of a hybrid memory system are disclosed.
Hieu Van Tran
Filed: 4 Nov 21
Utility
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21 Feb 23
Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 21 Mar 19
Utility
4nclel7032u9jb4sft8mictdtc43tyrcecb4wk1jt5m7ur3qa5
16 Feb 23
Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.
Hieu Van Tran, KHA NGUYEN, THUAN VU, HIEN PHAM, STANLEY HONG, STEPHEN TRINH
Filed: 5 Nov 21
Utility
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16 Feb 23
Numerous embodiments of output circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.
Hieu Van Tran, Thuan Vu
Filed: 8 Nov 21
Utility
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2 Feb 23
Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 21 Sep 22
Utility
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31 Jan 23
Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
Hieu Van Tran, Stanley Hong, Thuan Vu, Anh Ly, Hien Pham, Kha Nguyen, Han Tran
Filed: 3 Oct 18
Utility
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19 Jan 23
Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
Filed: 29 Jun 22
Utility
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27 Dec 22
Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system.
Xian Liu, Chunming Wang, Nhan Do, Hieu Van Tran
Filed: 11 Mar 21
Utility
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22 Dec 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
Filed: 22 Aug 22
Utility
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20 Dec 22
Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Vipin Tiwari, Nhan Do
Filed: 17 Sep 20