291 patents
Page 4 of 15
Utility
Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
15 Dec 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van TRAN, Thuan VU, Stephen TRINH, Stanley HONG, Anh LY, Steven LEMKE, Nha NGUYEN, Vipin TIWARI, Nhan DO
Filed: 22 Aug 22
Utility
Compensation For Reference Transistors And Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network
8 Dec 22
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Method of Improving Read Current Stability In Analog Non-volatile Memory by Post-program Tuning for Memory Cells Exhibiting Random Telegraph Noise
8 Dec 22
A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current.
VIKTOR MARKOV, ALEXANDER KOTOV
Filed: 21 Sep 21
Utility
Method of Reducing Random Telegraph Noise In Non-volatile Memory by Grouping and Screening Memory Cells
8 Dec 22
A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2.
Viktor Markov, ALEXANDER KOTOV
Filed: 22 Sep 21
Utility
Temperature compensation in an analog memory array by changing a threshold voltage of a selected memory cell in the array
6 Dec 22
Numerous embodiments are disclosed for providing temperature compensation in an analog memory array.
Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
Filed: 11 Nov 20
Utility
Programming analog neural memory cells in deep learning artificial neural network
6 Dec 22
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 3 Mar 21
Utility
Precision Tuning for the Programming of Analog Neural Memory In a Deep Learning Artificial Neural Network
1 Dec 22
Numerous examples of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
HIEU VAN TRAN, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
Filed: 27 Jul 22
Utility
Compensation for Reference Transistors and Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network
1 Dec 22
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Output Circuit for Analog Neural Memory In a Deep Learning Artificial Neural Network
24 Nov 22
Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Mark Reiten
Filed: 31 Aug 21
Utility
Split Array Architecture for Analog Neural Memory In a Deep Learning Artificial Neural Network
24 Nov 22
Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 30 Aug 21
Utility
Precise Data Tuning Method and Apparatus for Analog Neural Memory In an Artificial Neural Network
24 Nov 22
Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 27 Jul 22
Utility
Non-volatile Memory Cell Array Formed In a P-well In a Deep N-well In a P-substrate
24 Nov 22
Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well, which is formed in a deep n-well, which is formed in a p-substrate.
Hieu Van Tran, Nhan Do
Filed: 30 Aug 21
Utility
Configurable input blocks and output blocks and physical layout for analog neural memory in deep learning artificial neural network
22 Nov 22
Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells.
Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 21 Jun 19
Utility
Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
22 Nov 22
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 19 Sep 19
Utility
Non-volatile memory system using strap cells in source line pull down circuits
22 Nov 22
The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits.
Leo Xing, Chunming Wang, Xian Liu, Nhan Do, Guangming Lin, Yaohua Zhu
Filed: 19 Oct 20
Utility
System for converting neuron current into neuron current-based time pulses in an analog neural memory in a deep learning artificial neural network
15 Nov 22
Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 14 Mar 19
Utility
Method of forming split gate memory cells with thinner tunnel oxide
1 Nov 22
A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.
Jeng-Wei Yang, Man-Tang Wu, Boolean Fan, Nhan Do
Filed: 18 Feb 21
Utility
Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
25 Oct 22
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 2 Jul 20
Utility
Precision Tuning of a Page or Word of Non-volatile Memory Cells In an Analog Neural Memory System
20 Oct 22
Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
Hieu Van Tran, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
Filed: 1 Jul 22
Utility
Precision Tuning of a Page or Word of Non-volatile Memory Cells In an Analog Neural Memory System
20 Oct 22
Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
Hieu Van Tran, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
Filed: 4 Jul 22