291 patents
Page 5 of 15
Utility
Ultra-precise Tuning of Neural Memory Cells
20 Oct 22
Examples for ultra-precise tuning of a selected memory cell are disclosed.
Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'mani, Thuan Vu, Nhan Do, Vipin Tiwari
Filed: 27 Jun 22
Utility
Testing of Analog Neural Memory Cells In an Artificial Neural Network
6 Oct 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van TRAN, Thuan VU, Stephen TRINH, Stanley HONG, Anh LY, Steven LEMKE, Nha NGUYEN, Vipin TIWARI, Nhan DO
Filed: 15 Jun 22
Utility
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6 Oct 22
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates.
Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
Filed: 21 Jun 22
Utility
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20 Sep 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
Filed: 12 Sep 19
Utility
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15 Sep 22
A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate.
Leo Xing, CHUNMING WANG, XIAN LIU, NHAN DO, GUO XIANG SONG
Filed: 14 Jun 21
Utility
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13 Sep 22
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 3 Oct 18
Utility
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13 Sep 22
A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.
Jack Sun, Chunming Wang, Xian Liu, Andy Yang, Guo Xiang Song, Leo Xing, Nhan Do
Filed: 21 Dec 20
Utility
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1 Sep 22
A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.
Guo Xiang Song, Chunming Wang, Leo Xing, Xian Liu, Nhan Do
Filed: 4 Jun 21
Utility
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23 Aug 22
Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
Filed: 3 Jul 19
Utility
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11 Aug 22
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 2 May 22
Utility
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9 Aug 22
Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 14 Mar 19
Utility
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2 Aug 22
A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer.
Chunming Wang, Xian Liu, Nhan Do, Leo Xing, Guo Yong Liu, Melvin Diao
Filed: 20 Feb 20
Utility
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21 Jul 22
A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
Serguei Jourba, CATHERINE DECOBERT, FENG ZHOU, JINHO KIM, XIAN LIU, NHAN DO
Filed: 8 Apr 22
Utility
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19 Jul 22
Embodiments for ultra-precise tuning of a selected memory cell are disclosed.
Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'Mani, Thuan Vu, Nhan Do, Vipin Tiwari
Filed: 4 Aug 20
Utility
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19 Jul 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
Filed: 12 Sep 19
Utility
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5 Jul 22
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates.
Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
Filed: 18 Feb 21
Utility
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30 Jun 22
Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system.
Xian Liu, Chunming Wang, Nhan Do, Hieu Van Tran
Filed: 11 Mar 21
Utility
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14 Jun 22
Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region.
Feng Zhou, Xian Liu, Steven Lemke, Hieu Van Tran, Nhan Do
Filed: 13 Oct 20
Utility
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14 Jun 22
A memory device includes a semiconductor substrate with memory cell and logic regions.
Jinho Kim, Elizabeth Cuevas, Yuri Tkachev, Parviz Ghazavi, Bernard Bertello, Gilles Festes, Bruno Villard, Catherine Decobert, Nhan Do, Jean Francois Thiery
Filed: 23 Jun 20
Utility
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7 Jun 22
Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
Filed: 27 Mar 18