291 patents
Page 13 of 15
Utility
High density split-gate memory cell
18 May 20
A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer.
Nhan Do, Xian Liu, Vipin Tiwari, Hieu Van Tran
Filed: 19 Jan 16
Utility
Programming Methods For Neural Network Using Non-volatile Memory Array
13 May 20
An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses.
Farnood Merrikh BAYAT, Xinjie GUO, Dmitri STRUKOV, Nhan DO, Hieu Van TRAN, Vipin TIWARI, Mark REITEN
Filed: 17 Jan 20
Utility
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11 May 20
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 24 Aug 19
Utility
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4 May 20
A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 23 May 19
Utility
l1gk3mk1hzhck3czb5161h944fczj27hss4lnlnzqtcobl4scnnx
4 May 20
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
Filed: 18 Sep 19
Utility
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15 Apr 20
Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices.
HIEU VAN TRAN, ANH LY, THUAN VU, KHA NGUYEN, HIEN PHAM, STANLEY HONG, STEPHEN T. TRINH
Filed: 12 Dec 18
Utility
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15 Apr 20
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 20 Dec 18
Utility
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6 Apr 20
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
Filed: 26 Feb 19
Utility
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30 Mar 20
A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.
Hsuan Liang, Jeng-Wei Yang, Man-Tang Wu, Nhan Do, Hieu Van Tran
Filed: 22 Jul 18
Utility
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30 Mar 20
Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 15 May 19
Utility
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30 Mar 20
A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas.
Jeng-Wei Yang, Chun-Ming Chen, Man-Tang Wu, Chen-Chih Fan, Nhan Do
Filed: 19 Sep 18
Utility
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23 Mar 20
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second.
Vipin Tiwari, Nhan Do, Hieu Van Tran
Filed: 19 Dec 17
Utility
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23 Mar 20
A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate.
Chunming Wang, Andy Liu, Xian Liu, Leo Xing, Melvin Diao, Nhan Do
Filed: 14 Oct 18
Utility
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9 Mar 20
A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance.
Xiaozhou Qian, Kai Man Yue, Guang Yan Luo
Filed: 29 Aug 18
Utility
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9 Mar 20
A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output.
Vipin Tiwari, Nhan Do
Filed: 1 Jul 18
Utility
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2 Mar 20
A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver.
Vipin Tiwari, Hieu Van Tran, Nhan Do, Mark Reiten
Filed: 20 Jun 18
Utility
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2 Mar 20
A memory array with memory cells arranged in rows and columns.
Vipin Tiwari, Nhan Do
Filed: 20 Aug 18
Utility
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26 Feb 20
A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region.
Viktor Markov, Alexander Kotov
Filed: 11 Dec 18
Utility
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26 Feb 20
Numerous embodiments are disclosed for a configurable hardware system for use in an analog neural memory system for a deep learning neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 5 Nov 18
Utility
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26 Feb 20
Numerous embodiments are disclosed for providing temperature compensation and leakage compensation for an analog neuromorphic memory system used in a deep learning neural network.
Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
Filed: 6 Nov 18