291 patents
Page 12 of 15
Utility
Flash memory cell and associated decoders
10 Aug 20
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells.
Hieu Van Tran, Anh Ly, Thuan Vu
Filed: 15 Mar 18
Utility
Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
10 Aug 20
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 20 Dec 18
Utility
y93mkmzkbsrm6tgqtlmzxbch16h6db8b4lx0k
29 Jul 20
A memory device includes a plurality of memory cells and a controller.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
03bpynuyl9xr1zqf8 wtm
29 Jul 20
A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
dzy5pel4qn77m7t829pwo19 gsq7jxj6us9dnhcctkaj7whipbw5kpd9a4dr
29 Jul 20
Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 20 Mar 19
Utility
850nuaz5tjyneoww3gxpl88067 9tlk0edtcy7xiwe3jqezipt3rruo
29 Jul 20
Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 20 Mar 19
Utility
eowh65byaqe4pzymi827zhrtlvw2ft6jvq gcdlpp6z49xm9dhsi10
27 Jul 20
A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 4 Jul 18
Utility
npf744ztg5vpsqxixon4gvipcsyaifz7mjc3 z9duhq3w0q0l
22 Jul 20
Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 13 Mar 19
Utility
yt4b8xkov18rfaqal1u1jv8jcegd1ale
22 Jul 20
Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 13 Mar 19
Utility
33b6i7fa8jfjj8aguw38g1fg101g kz7oertkmd1mg9im11n1
22 Jul 20
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
i1qupwr73wy6pcjn72rh3k4gukuir0b053bdwibn
20 Jul 20
A memory device includes a plurality of memory cells and a controller.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
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13 Jul 20
A memory device with a memory cell and control circuitry.
Yuri Tkachev, Alexander Kotov, Nhan Do
Filed: 3 Dec 18
Utility
zly4yodxgxk3q2ren5vp42dz1aiuwi672znmwxpf x0bohth5ffihs
13 Jul 20
A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate.
Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Chien-Sheng Su, Nhan Do
Filed: 21 Oct 18
Utility
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29 Jun 20
A neural network device having a first plurality of synapses that includes a plurality of memory cells.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
w7rwdob6p0wprsvoccwtdya3arja6rxmctt3dgglh13eidfdnk
29 Jun 20
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second.
Vipin Tiwari, Nhan Do, Hieu Van Tran
Filed: 5 Feb 20
Utility
e2hm770d693gsbq9bs3mptrq1pl769rlhtr2nwcorbnr3ibkmkgdv76l7
22 Jun 20
A system and method are disclosed for performing address fault detection in a flash memory system.
Hieu Van Tran, Xian Liu, Nhan Do
Filed: 25 Aug 19
Utility
d7wmf9jvc7vj90 w7qk3mw5a9eh91itu
3 Jun 20
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second.
VIPIN TIWARI, NHAN DO, HIEU VAN TRAN
Filed: 5 Feb 20
Utility
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3 Jun 20
A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin.
Feng Zhou, JINHO KIM, XIAN LIU, SERGUEI JOURBA, CATHERINE DECOBERT, NHAN DO
Filed: 2 Dec 18
Utility
80upyvejsvcmod7c101tk bpyhlyxtcgvtkx8xiaylggseojpkn
3 Jun 20
A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between.
CATHERINE DECOBERT, HIEU VAN TRAN, NHAN DO
Filed: 2 Dec 18
Utility
io5nrtj9j4hquzki85htyrj6obqvs
3 Jun 20
A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 2 Dec 18