291 patents
Page 12 of 15
Utility
Flash memory cell and associated decoders
10 Aug 20
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells.
Hieu Van Tran, Anh Ly, Thuan Vu
Filed: 15 Mar 18
Utility
Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
10 Aug 20
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 20 Dec 18
Utility
Memory Device And Method For Varying Program State Separation Based Upon Frequency Of Use
29 Jul 20
A memory device includes a plurality of memory cells and a controller.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
Neural Network Classifier Using Array Of Stacked Gate Non-volatile Memory Cells
29 Jul 20
A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
Precision Programming Circuit For Analog Neural Memory In Deep Learning Artificial Neural Network
29 Jul 20
Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 20 Mar 19
Utility
Algorithms and Circuitry for Verifying a Value Stored During a Programming Operation of a Non-volatile Memory Cell In an Analog Neural Memory In Deep Learning Artificial Neural Network
29 Jul 20
Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 20 Mar 19
Utility
Split gate non-volatile memory cells with three-dimensional FinFET structure
27 Jul 20
A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 4 Jul 18
Utility
Power Management For An Analog Neural Memory In A Deep Learning Artificial Neural Network
22 Jul 20
Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 13 Mar 19
Utility
System for Converting Neuron Current into Neuron Current-based Time Pulses In an Analog Neural Memory In a Deep Learning Artificial Neural Network
22 Jul 20
Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network.
Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
Filed: 13 Mar 19
Utility
Neural Network Classifier Using Array Of Three-Gate Non-volatile Memory Cells
22 Jul 20
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
Memory device and method for varying program state separation based upon frequency of use
20 Jul 20
A memory device includes a plurality of memory cells and a controller.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
Method of programming a split-gate flash memory cell with erase gate
13 Jul 20
A memory device with a memory cell and control circuitry.
Yuri Tkachev, Alexander Kotov, Nhan Do
Filed: 3 Dec 18
Utility
Non-volatile split gate memory cells with integrated high K metal control gates and method of making same
13 Jul 20
A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate.
Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Chien-Sheng Su, Nhan Do
Filed: 21 Oct 18
Utility
Neural network classifier using array of two-gate non-volatile memory cells
29 Jun 20
A neural network device having a first plurality of synapses that includes a plurality of memory cells.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 10 Apr 19
Utility
System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
29 Jun 20
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second.
Vipin Tiwari, Nhan Do, Hieu Van Tran
Filed: 5 Feb 20
Utility
Address fault detection in a flash memory system
22 Jun 20
A system and method are disclosed for performing address fault detection in a flash memory system.
Hieu Van Tran, Xian Liu, Nhan Do
Filed: 25 Aug 19
Utility
System and Method for Minimizing Floating Gate to Floating Gate Coupling Effects During Programming In Flash Memory
3 Jun 20
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second.
VIPIN TIWARI, NHAN DO, HIEU VAN TRAN
Filed: 5 Feb 20
Utility
Split Gate Non-volatile Memory Cells With FINFET Structure And HKMG Memory And Logic Gates, And Method Of Making Same
3 Jun 20
A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin.
Feng Zhou, JINHO KIM, XIAN LIU, SERGUEI JOURBA, CATHERINE DECOBERT, NHAN DO
Filed: 2 Dec 18
Utility
Memory Cell With Floating Gate, Coupling Gate And Erase Gate, And Method Of Making Same
3 Jun 20
A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between.
CATHERINE DECOBERT, HIEU VAN TRAN, NHAN DO
Filed: 2 Dec 18
Utility
FINFET-Based Split Gate Non-volatile Flash Memory With Extended Source Line FINFET, and Method Of Fabrication
3 Jun 20
A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 2 Dec 18