997 patents
Page 41 of 50
Utility
Electroconductive support body and method for manufacturing same, electrophotographic photoreceptor, and electrophotographic device
4 May 20
An electrically conductive support for use in an electrophotographic photoreceptor includes a cylindrical main body having a first end and a second end opposite to the first end in an axial direction of the main body.
Hirotaka Kobayashi
Filed: 22 Aug 19
Utility
Semiconductor device and semiconductor device manufacturing method
27 Apr 20
A semiconductor device is provided, in order to prevent tilt of a terminal pin in the semiconductor device with a printed board in which the terminal pin is pressed, the semiconductor device comprising a printed board, a plurality of pins pressed in the printed board, a resin block in which a plurality of through holes are formed, the plurality of pins respectively pressed in the plurality of through holes, and a resin case covering at least a part of the printed board and the resin block.
Shin Soyano
Filed: 23 Nov 17
Utility
Driving device and switching device
27 Apr 20
In recent years, it has been desired to further shorten the dead time.
Kunio Matsubara, Tsuyoshi Nagano
Filed: 2 Jun 19
Utility
Optical touch panel and automatic vending machine
27 Apr 20
An optical touch panel includes: a pair of retroreflective plates that are arranged inside at least a left and right pair of frame portions facing each other in a rectangular frame; a plurality of detectors that are arranged at four corners of the rectangular frame, the detectors being configured to irradiate infrared rays to, at least, the retroreflective plates, and to generate detection images based on reflection light from the retroreflective plates; and an operation determining unit configured to detect a touch position based on the detection images generated by the detectors.
Makoto Nakamura, Shimoto Ichihara, Tomonori Maekawa, Yuki Wagatsuma, Shinya Nakanishi, Yoshito Shibata
Filed: 27 Dec 17
Utility
Method of manufacturing semiconductor device
27 Apr 20
Along dicing lines, cutting grooves that reach a rear surface from a front surface are formed by a first dicing blade in a semiconductor wafer, completely separating the semiconductor wafer into individual semiconductor chips by the cutting grooves.
Takashi Shimada
Filed: 21 Jan 19
Utility
Semiconductor device, method for manufacturing semiconductor device, and interface unit
27 Apr 20
A semiconductor device includes a base plate, a plurality of semiconductor units provided in parallel on the base plate, the plurality of semiconductor units implementing a pair, each semiconductor unit including a semiconductor chip and a rod-shaped unit-side control terminal, the unit-side control terminal being connected to the semiconductor chip, the unit-side control terminal extending opposite to the base plate; and an interface unit including a box-shaped accommodating portion, the accommodating portion being provided on the plurality of semiconductor units, the accommodating portion including an internal wiring and a rod-shaped external-connecting control terminal, the internal wiring being connected to each of the plurality of the unit-side control terminals extending from the plurality of semiconductor units, the external-connecting control terminal extending to the outside opposite to the semiconductor units, the external-connecting control terminal being connected to the internal wiring.
Motohito Hori, Yuki Inaba, Yoshinari Ikeda, Tetsuya Sunago, Michihiro Inaba
Filed: 22 Mar 18
Utility
Semiconductor device and method for manufacturing semiconductor device
27 Apr 20
A semiconductor device includes a plurality of broad buffer layers provided in a drift layer.
Michio Nemoto, Takashi Yoshimura
Filed: 26 Jul 18
Utility
Semiconductor device
27 Apr 20
A semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion.
Tatsuya Naito
Filed: 28 Sep 17
Utility
Silicon carbide semiconductor substrate, method of manufacturing silicon carbide semiconductor substrate, semiconductor device, and method of manufacturing semiconductor device
20 Apr 20
A silicon carbide semiconductor substrate includes a silicon carbide substrate of a first conductivity type, an epitaxial layer of the first conductivity type provided on a front surface of the silicon carbide substrate, an impurity concentration of the epitaxial layer being 1×1017/cm3 to 1×1018/cm3, and a film thickness of the epitaxial layer being 1 μm to 5 μm.
Takeshi Tawara
Filed: 29 Nov 17
Utility
Method of manufacturing semiconductor device
20 Apr 20
A photoresist is applied to a front surface of a semiconductor wafer rotating at a predetermined rotational speed and a photoresist film having a predetermined thickness is formed and dried.
Naoko Kodama
Filed: 26 Nov 18
Utility
Semiconductor device and fabrication method thereof
20 Apr 20
A semiconductor device including a connection terminal that is electrically connected to a semiconductor chip, a bus bar with an opening through which the connection terminal passes, and a fusing portion including a jointing portion, which is provided over an upper surface of the bus bar from an upper part of the connection terminal that is positioned above the upper surface of the bus bar by making the connection terminal pass through the opening of the bus bar, is provided.
Koji Ichikawa, Kento Shirata
Filed: 24 Jun 18
Utility
Semiconductor device and method of manufacturing semiconductor device
20 Apr 20
A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion.
Souichi Yoshida, Seiji Noguchi, Kenji Kouno, Hiromitsu Tanabe
Filed: 24 Aug 17
Utility
RC-IGBT and manufacturing method thereof
20 Apr 20
An RC-IGBT having a transistor portion and diode portion is provided.
Tatsuya Naito
Filed: 27 Aug 18
Utility
Semiconductor device having semiconductor regions with an interval therebetween in a gate pad region
20 Apr 20
A vertical MOSFET having a trench gate structure includes an n−-type drift layer and a p-type base layer formed by epitaxial growth.
Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoyuki Ohse
Filed: 22 Oct 18
Utility
Scrubber wastewater treatment method and scrubber wastewater treatment device
13 Apr 20
A scrubber wastewater treatment method, according to one possible embodiment, includes obtaining a measurement of a turbidity or of a suspended substance concentration of scrubber wastewater and, upon determining that measurement of turbidity or suspended substance concentration is within a certain range, performing treatment.
Yosuke Hanai, Nami Ishikawa, Yasuzo Sakai
Filed: 6 Jun 17
Utility
Semiconductor device
13 Apr 20
A semiconductor device having an input terminal and an output terminal.
Morio Iwamizu, Shinji Yamashina
Filed: 28 Jan 19
Utility
Semiconductor device manufacturing method and semiconductor device
13 Apr 20
To enhance efficiency of a process of implanting impurities into a silicon carbide semiconductor layer.
Katsushi Nishiyama, Masayuki Miyazaki, Shoji Kitamura
Filed: 22 May 18
Utility
Semiconductor package
13 Apr 20
A semiconductor package is provided, including: a package body; and a plurality of lead terminals exposed from each of at least three side surfaces of the package body, wherein the plurality of lead terminals include: a plurality of lead terminals exposed from a first side surface, half or more of which have tips pointing in a direction along the first side surface; a plurality of lead terminals exposed from a second side surface, all of which have tips pointing in a direction along a direction orthogonal to the second side surface; and a plurality of lead terminals exposed from a third side surface, half or more of which have tips pointing in a direction along the third side surface, or all of which have tips pointing in a direction along a direction orthogonal to the third side surface.
Hiroki Kogawa, Takahiro Nishijima, Takashi Katsuki, Tadahiko Sato
Filed: 25 Sep 18
Utility
Semiconductor device
13 Apr 20
Provided is a semiconductor device including transistor regions and diode regions each extending from a given one edge of an active region to a different edge of the active region, a first-conductivity-type pad well region in contact with a gate runner region shaped like a rectangular ring and provided within the gate runner region, and first-conductivity-type collector regions provided in the transistor regions in a one-to-one correspondence and second-conductivity-type cathode regions provided in the diode regions in a one-to-one correspondence.
Akinori Kanetake, Misaki Takahashi
Filed: 5 Dec 18
Utility
Silicon carbide based power semiconductor device with low on voltage and high speed characteristics
13 Apr 20
A semiconductor device includes in an active region in which current flows, an n+-type silicon carbide epitaxial layer of a low concentration and formed on an n+-type silicon carbide substrate; a p-type channel region constituting a channel region; a trench contacting the p-type channel region and having embedded therein an oxide film and a gate electrode; a p+-type base layer arranged beneath the trench; a third n-type CSL layer region contacting the p-type channel region; a second n-type CSL layer region having a maximum impurity concentration higher than that of the third n-type CSL layer region, the maximum impurity concentration being farther on a substrate front side than a top of the p+-type base layer arranged beneath the trench is; and a first n-type CSL layer region contacting the second n-type CSL layer region and having a maximum impurity concentration lower than that of the second n-type CSL layer region.
Yusuke Kobayashi, Akimasa Kinoshita, Shinsuke Harada
Filed: 31 Jul 17