386 patents
Page 17 of 20
Utility
Sample Rod Center Slab Resistivity Measurement During Single Crystal Silicon Ingot Production
24 Jun 20
Methods for forming single crystal silicon ingots with improved resistivity control are disclosed.
HyungMin Lee, JaeWoo Ryu, Richard Phillips, YoungJung Lee, Carissima Marie Hudson
Filed: 20 Dec 18
Utility
Sample Rod Center Slab Resistivity Measurement With Four-Point Probe During Single Crystal Silicon Ingot Production
24 Jun 20
Methods for forming single crystal silicon ingots with improved resistivity control are disclosed.
HyungMin Lee, JaeWoo Ryu, Richard Phillips, YoungJung Lee, Carissima Marie Hudson
Filed: 20 Dec 18
Utility
Ingot Puller Apparatus that Include A Doping Conduit With A Porous Partition Member For Subliming Solid Dopant
17 Jun 20
Ingot puller apparatus for preparing silicon ingots that include a dopant feed system are disclosed.
Roberto Scala, Stephan Haringer, Franco Battan
Filed: 13 Dec 18
Utility
Methods For Preparing a Doped Ingot
17 Jun 20
Ingot puller apparatus for preparing silicon ingots that include a dopant feed system are disclosed.
Roberto Scala, Stephan Haringer, Franco Battan
Filed: 13 Dec 18
Utility
Silicone Carbide Crystals and Manufacturing Method Thereof
17 Jun 20
A silicon carbide crystal and a manufacturing method thereof are provided.
CHING-SHAN LIN, JIAN-HSIN LU, CHIEN-CHENG LIOU, I-CHING LI
Filed: 23 Jun 19
Utility
Cleave systems, mountable cleave monitoring systems, and methods for separating bonded wafer structures
8 Jun 20
Cleave systems for separating bonded wafer structures, mountable cleave monitoring systems and methods for separating bonded wafer structures are disclosed.
Justin Scott Kayser, John Francis Valley, James Dean Eoff
Filed: 8 Jan 18
Utility
Slurry Sprayers, Adjustable Supports for Same, and Methods for Slicing a Silicon Ingot
3 Jun 20
A slurry sprayer for supplying a slurry to a wire saw during ingot slicing is disclosed.
Chia Ming Liu, Chien Ming Chen, Jui Hung Wang, Hao Chen
Filed: 26 Nov 19
Utility
Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
1 Jun 20
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided.
Igor Peidous, Illaria Katia Marianna Pellicano
Filed: 20 Aug 18
Utility
Methods and system for controlling a surface profile of a wafer
18 May 20
Methods for controlling the surface profiles of wafers sliced from an ingot with a wire saw include measuring an amount of displacement of a sidewall of a frame of the wire saw.
Peter D. Albrecht, Carlos Zavattari, Sumeet S. Bhagavat, Vandan Tanna, Uwe Hermes
Filed: 15 May 19
Utility
Methods and systems for polishing pad control
18 May 20
A method for varying a removal profile of a silicon wafer during polishing using a polishing apparatus is provided.
Emanuele Corsi, Ezio Bovio
Filed: 22 Jun 16
Utility
Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
18 May 20
A semiconductor on insulator multilayer structure is provided.
Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
Filed: 11 Nov 18
Utility
Direct formation of hexagonal boron nitride on silicon based dielectrics
18 May 20
A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein.
Vikas Berry, Sanjay Behura, Phong Nguyen, Michael R. Seacrist
Filed: 27 Apr 17
Utility
Direct Formation of Hexagonal Boron Nitride on Silicon Based Dielectrics
13 May 20
A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein.
Vikas Berry, Sanjay Behura, Phong Nguyen, Michael R. Seacrist
Filed: 23 Dec 19
Utility
Direct Formation of Hexagonal Boron Nitride on Silicon Based Dielectrics
13 May 20
A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein.
Vikas Berry, Sanjay Behura, Phong Nguyen, Michael R. Seacrist
Filed: 23 Dec 19
Utility
Wafer nanotopography metrology for lithography based on thickness maps
27 Apr 20
A method for lithography nanotopography metrology is provided.
John F. Valley
Filed: 27 Aug 18
Utility
Manufacturing Method of High Electron Mobility Transistor
22 Apr 20
A manufacturing method of a high electron mobility transistor includes providing an epitaxial stacked structure, wherein the epitaxial stacked structure includes a semiconductor substrate, a buffer layer formed on the semiconductor substrate, a channel layer formed on the buffer layer, an intermediate layer formed on the channel layer, and a barrier layer formed on the intermediate layer; forming a source and a drain on the barrier layer; performing a microwave annealing process, wherein the conditions of the microwave annealing process include a temperature between 450° C. and 550° C., a frequency between 5.8 GHz and 6.2 GHz, and a time between 150 seconds and 250 seconds; and forming a gate on the barrier layer between the source and the drain.
Hsien-Chin Chiu, Ying-Ru Shih
Filed: 21 Oct 18
Utility
High Resistivity Silicon-on-insulator Substrate Having Enhanced Charge Trapping Efficiency
22 Apr 20
A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type.
Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Qingmin Liu
Filed: 17 Dec 19
Utility
Method of Depositing Charge Trapping Polycrystalline Silicon Films on Silicon Substrates with Controllable Film Stress
22 Apr 20
A semiconductor on insulator multilayer structure is provided.
Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
Filed: 18 Dec 19
Utility
Semiconductor on Insulator Structure Comprising a Buried High Resistivity Layer
22 Apr 20
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided.
Igor Peidous, Andrew M. Jones, Srikanth Kommu, Horacio Josue Mendez
Filed: 18 Dec 19
Utility
III-nitride epitaxial structure
20 Apr 20
An epitaxial structure includes a substrate, a buffer layer, a channel layer, an intermediate layer, and a barrier layer.
Jia-Zhe Liu, Yen-Lun Huang, Ying-Ru Shih
Filed: 21 Nov 18