1577 patents
Page 5 of 79
Utility
Semiconductor Device and Method of Manufacturing the Same
2 Nov 23
A pad electrode is formed in an uppermost wiring layer of a multilayer wiring layer formed on a semiconductor substrate.
Takashi MORIYAMA
Filed: 2 Feb 23
Utility
Semiconductor Device
2 Nov 23
An improved power MOSFET having a super junction structure is disclosed.
Yuta NABUCHI, Akihiro SHIMOMURA
Filed: 10 Jan 23
Utility
Semiconductor Device and Method of Manufacturing the Same
26 Oct 23
A ferroelectric memory cell includes a paraelectric film formed on a semiconductor substrate and a ferroelectric layer formed on the paraelectric film.
Kazuyuki OMORI, Tadashi YAMAGUCHI
Filed: 7 Mar 23
Utility
Semiconductor Device
26 Oct 23
A semiconductor device includes a plurality of resistive films arranged on an interlayer dielectric film.
Nobuhito SHIRAISHI, Yasuo MORIMOTO, Yoshihiro FUNATO
Filed: 2 Feb 23
Utility
Semiconductor Device
26 Oct 23
A semiconductor device includes first and second interlayer insulating films, first and second wirings, and a resistor film.
Nobuhito SHIRAISHI, Naohito SUZUMURA
Filed: 27 Feb 23
Utility
Semiconductor device and method of manufacturing the same
24 Oct 23
A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film.
Hirokazu Sayama, Fumihiko Hayashi, Junjiro Sakai
Filed: 6 Oct 22
Utility
Semiconductor device
24 Oct 23
The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film.
Kodai Ozawa, Sho Nakanishi
Filed: 1 Nov 21
Utility
Semiconductor device and control system
24 Oct 23
Detection transistor MNd flows a detection current IdN to a current path CP1n when an output voltage Vo generated in a load terminal PN1 is than a ground voltage GND.
Naohiro Yoshimura, Makoto Tanaka
Filed: 12 Sep 22
Utility
Semiconductor device and method for controlling body bias thereof
24 Oct 23
A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided.
Hiroyuki Watanabe, Hideshi Shimo
Filed: 8 Sep 22
Utility
Image sensor
24 Oct 23
An image sensor including an ADC circuit receiving pixel data to be supplied in parallel from the a pixel array, outputting a reference signal in accordance with a digital code, comparing the reference signal and the pixel data, and outputting the digital code at which the reference signal and the pixel data have a predetermined relation, the ADC circuit including a ramp-signal generating circuit outputting a ramp signal having a gradient with respect to change of the digital code, the gradient being different between when the digital code is in a first range and when the digital code is in a second range different from the first range and an attenuator receiving the ramp signal to be supplied and outputting the reference signal having a gradient being the same between when the digital code is in the first range and when the digital code is in the second range.
Fukashi Morishita
Filed: 27 Jun 22
Utility
Device and Method of Secure Decryption by Virtualization and Translation of Physical Encryption Keys
19 Oct 23
Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.
Ahmad NASSER, Eric WINDER
Filed: 16 Jun 23
Utility
Semiconductor Device
19 Oct 23
A semiconductor device having an electrically writable or erasable non-volatile memory and a control circuit for executing mode control of a write operation and an erase operation of the non-volatile memory, in which the non-volatile memory has a rewrite suspension/recovery control circuit: responding to a suspension request signal from the control unit that requests a suspension of a rewrite operation; responding to an operation for suspending an application of a write voltage or an erase voltage and a recovery request signal from the control unit that requests a recovery from the suspension of the rewrite operation; controlling an operation for recovery from the suspension of the voltage application; and outputting a rewrite interruption/return control circuit that outputs to the control circuit a voltage application stop flag at a voltage application stop of the write voltage or erase voltage, and a rewrite information holding circuit that holds write position information for identifying a selection line to which a write voltage is applied at a response time of a suspension request signal.
Hirofumi HEBISHIMA
Filed: 12 Apr 23
Utility
Semiconductor Device
19 Oct 23
An inductor to which a first potential is applied is surrounded by a first wiring connected with the inductor, and a pad connected with a second wiring, to which a second potential different from the first potential is applied, is disposed outside the second wiring such that the first wiring is surrounded by the second wiring.
Yasutaka NAKASHIBA, Takayuki IGARASHI
Filed: 27 Feb 23
Utility
Electronic Device and Semiconductor Device
19 Oct 23
The wiring board has a first region overlapping a first semiconductor device and a second region not overlapping each of the first semiconductor device and a second semiconductor device.
Shuuichi KARIYAZAKI, Ryuichi OIKAWA
Filed: 14 Apr 22
Utility
Designing Method and Semiconductor Device
19 Oct 23
The designing method according to an embodiment of the present invention is a method of designing a transmission line portion coupled between a transmission unit and a receiving unit, and transmitting a signal from the transmission unit to the receiving unit.
Ryuichi OIKAWA
Filed: 14 Apr 22
Utility
Semiconductor Device
19 Oct 23
A semiconductor device includes first and second active cell regions and an inactive cell region between the first and second active cell regions, wherein each of the first and second active cell regions comprises: a trench gate; a first trench emitter; a first hole barrier layer of a first conductivity type formed between the trench gate and the first trench emitter; a base layer of a second conductivity type formed on upper portion of the first hole barrier layer; an emitter layer of the first conductivity type formed on upper portion of the base layer; a latch-up prevention layer of the second conductivity type formed on upper portion of the first hole barrier layer, wherein the inactive cell region comprises: a second trench emitter; a first floating layer of the second conductivity type formed between the trench gate of the first active cell region and the second trench emitter.
Nao NAGATA
Filed: 14 Apr 22
Utility
Semiconductor Device and Method of Manufacturing the Same
19 Oct 23
A source diffusion layer and a base diffusion layer are formed in regions of a semiconductor substrate located between a trench gate electrode and a trench emitter electrode that are spaced apart from each other.
Kouichi KONISHI
Filed: 10 Jan 23
Utility
Semiconductor Device
19 Oct 23
A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench.
Katsumi EIKYU, Atsushi SAKAI, Yotaro GOTO
Filed: 18 Apr 22
Utility
Network management and communication protocol analysis for network devices in a network
17 Oct 23
A conventional network managing method has a problem that there is a high possibility that a setting error of communication software occurs.
Tatsuya Kato
Filed: 10 Feb 22
Utility
Systems Including Bounding Box Checker for Object Detection Marking
12 Oct 23
Systems and methods for evaluating a set of bounding boxes in a blended image are described.
Shijia GUO, Stefan GELDREICH
Filed: 12 Apr 22