997 patents
Page 22 of 50
Utility
Semiconductor device with field stop layer and semiconductor device manufacturing method thereof
19 Oct 21
First and second n-type field stop layers in an n− drift region come into contact with a p+ collector layer.
Tomonori Mizushima
Filed: 15 Mar 13
Utility
Semiconductor device
19 Oct 21
A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, first base regions of the second conductivity type, second base regions of the second conductivity type, gate insulating films, gate electrodes, a first electrode, a second electrode, and trenches.
Syunki Narita
Filed: 27 Feb 20
Utility
Snubber circuit and power conversion apparatus
19 Oct 21
A snubber circuit is provided, including N charge paths having a positive-side capacitor, a first diode, and a negative-side capacitor connected in series between positive-side wiring and negative-side wiring, and conducts current from a positive side to a negative side; N+1 discharge paths including a second diode connected between a negative-side capacitor in kth charge path and a positive-side capacitor in k+1th charge path and conducts current from a negative side to a positive side via a negative-side capacitor or a positive-side capacitor; other charge paths including an inductor between a positive-side capacitor in ith charge path and a negative-side capacitor in i+1th charge path and conducts current from the positive side to the negative side, and the positive-side capacitor and negative-side capacitor included in the other charge path have a larger capacity than each of the positive-side capacitor and negative-side capacitor not included in the other charge path.
Ryuji Yamada
Filed: 24 Jun 20
Utility
Evaluation method, estimation method, evaluation apparatus, and combined evaluation apparatus
12 Oct 21
The radiated noise of a semiconductor device is conveniently evaluated, and the radiated noise of an apparatus equipped with the semiconductor device is estimated.
Hiroki Katsumata, Michio Tamate, Miwako Fujita, Tamiko Asano, Yuhei Suzuki, Takashi Kaimi, Yuta Sunasaka, Tadanori Yamada, Ryu Araki, Bao Cong Hiu
Filed: 29 Jan 19
Utility
Photoconductor having interlayer for hole injection promotion
12 Oct 21
A photoconductor for electrophotography includes a base member; an anodic oxide coating provided on the base member and having a film thickness of 2 to 10 μm; an interlayer provided on the anodic oxide coating and containing a vinyl chloride-vinyl acetate copolymer resin and having a film thickness of 0.02 to 0.3 μm; and a photosensitive layer including a charge transport layer formed on the interlayer and containing a charge transport material and a first resin binder, and a charge generation layer laminated on the charge transport layer and containing a charge generation material, a hole transport material, a first electron transport material that is a naphthalenetetracarboxylic diimide compound, a second electron transport material that is an azoquinone compound, a diphenoquinone compound, or a stilbenequinone compound and that has a mobility of 17×10−8 cm2/V·s or more, and a second resin binder.
Seizo Kitagawa, Kazuya Saito, Kazuki Nebashi, Hiroshi Emori, Masaru Takeuchi
Filed: 3 Jan 20
Utility
Method of manufacturing semiconductor integrated circuit
12 Oct 21
A semiconductor integrated circuit includes: implanting impurity ions of a p-type at different implantation positions by multiple implantation in a part of an upper portion of a semiconductor layer of an n−-type to form first ion implantation regions; implanting the impurity ions of the p-type at different implantation positions by multiple implantation in another part of the upper portion of the semiconductor layer to form second ion implantation regions; activating the impurity ions in the first ion implantation regions to form a well region, and activating the impurity ions in the second ion implantation regions to form a body region; forming a control element including first and second terminal regions of the n+-type in an upper portion of the well region; and forming an output-stage element including an output terminal region of the n+-type in an upper portion of the body region to be controlled by the control element.
Yoshiaki Toyoda
Filed: 24 Dec 19
Utility
Solder material for semiconductor device
12 Oct 21
A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range.
Hirohiko Watanabe, Shunsuke Saito, Yoshitaka Nishimura, Fumihiko Momose
Filed: 5 Jun 20
Utility
Semiconductor device, lead frame, and method for manufacturing semiconductor device
12 Oct 21
Provided is a semiconductor device that can improve yield and non-defective rate by obtaining the thickness of a melt-bonding material and suppressing inclination of a circuit board.
Naoki Saegusa
Filed: 25 Apr 19
Utility
Manufacturing method of semiconductor module
12 Oct 21
A manufacturing method of a semiconductor module including a trimming resistance element and a plurality of transistor chips connected mutually in parallel, in which gate electrodes are connected to one end of the trimming resistance element, including: measuring elapsed time and a gate-source voltage value when a predetermined gate current is injected into the gate electrodes and a predetermined drain current flow; calculating a gate-source capacity on the basis of the gate-source voltage value; determining a compensation gate resistance value on the basis of the gate-source voltage value and the gate-source capacity; and changing a resistance value of the trimming resistance element such that the resistance value of the trimming resistance element is conformed to the compensation gate resistance value.
Masashi Hoya
Filed: 29 Jan 20
Utility
Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
12 Oct 21
A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a first semiconductor region of the first conductivity type.
Keishirou Kumada, Yuichi Hashizume, Yasuyuki Hoshi, Yoshihisa Suzuki
Filed: 23 Aug 19
Utility
Snubber circuit and power conversion apparatus
12 Oct 21
Provided is a snubber circuit comprising N parallel charging paths each having a positive-side capacitor, a first diode, and a negative-side capacitor sequentially connected in series between a positive-side terminal and a negative-side terminal, and configured to conduct current from the positive-side terminal toward the negative-side terminal; (N+1) parallel discharging paths each having a second diode connected between the negative-side terminal or the negative-side capacitor of kth charging path of N charging paths and the positive-side capacitor of (k+1)th charging path of N charging paths or the positive-side terminal, and configured to counduct current from the negative-side terminal toward the positive-side terminal via at least one of the negative-side capacitor and the positive-side capacitor; and at least one auxiliary capacitor each being connected in parallel to at least one of the N first diodes included on N charging paths and (N+1) second diodes included on (N+1) discharging paths.
Ryuji Yamada
Filed: 24 Jun 20
Utility
High voltage integrated circuit
12 Oct 21
In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors.
Masaharu Yamaji
Filed: 1 Aug 19
Utility
Cooling structure for coil component
5 Oct 21
A coil device with a cooling structure includes: a coil unit that has a core structure having one or more leg parts and one or more coils wound around the one or more leg parts; and a flow-rectifying member having a flat plate portion covering a face of the one or more coils and flow-rectifying ribs inwardly protruding from an inner surface of the flat plate portion, the flow-rectifying ribs extending in a direction parallel to center axes of the one or more coils and being positioned to face side boundaries of the face of the one or more coils.
Kiyoshi Takahashi
Filed: 5 Jul 17
Utility
Method of manufacturing silicon carbide semiconductor device
5 Oct 21
On a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate is formed.
Keiji Okumura
Filed: 28 Jan 20
Utility
Semiconductor device
5 Oct 21
A semiconductor device is provided, including a semiconductor substrate, wherein the semiconductor substrate has: a diode region; a transistor region; and a boundary region that is positioned between the diode region and the transistor region, the boundary region includes a defect region that is provided: at a predetermined depth position on a front surface-side of the semiconductor substrate; and to extend from an end portion of the boundary region adjacent to the diode region toward the transistor region, at least part of the boundary region does not include a first conductivity-type emitter region exposed on a front surface of the semiconductor substrate, and the transistor region does not have the defect region below a mesa portion that is sandwiched by two adjacent trench portions, and closest to the boundary region among the mesa portions having the emitter region.
Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi, Kaname Mitsuzuka, Daisuke Ozaki, Akinori Kanetake
Filed: 29 Nov 19
Utility
Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
5 Oct 21
A trench gate MOSFET has at an n-type current spreading region between an n−-type drift region and a p-type base region, a first p+-type region facing a bottom of a trench, and a second p+-type region disposed between adjacent trenches.
Akimasa Kinoshita, Keiji Okumura
Filed: 23 Aug 19
Utility
Semiconductor device and manufacturing method
5 Oct 21
Provided is a semiconductor device, wherein at least one mesa portion contacting a gate trench portion thereof comprises: a first conductivity type emitter region with a doping concentration higher than a drift region, exposed on the top of the substrate and contacting the gate trench portion; a second conductivity type base region under the emitter region, contacting the trench portion, having a first peak in a doping concentration distribution in a depth direction of the substrate; a first conductivity type accumulation region under the base region, having a doping concentration higher than the drift region; and a second conductivity type intermediate region at a depth position between the base region and the accumulation region, having at least one of a second peak and a kink portion from the first peak to a depth position of a bottom of the trench portion in the doping concentration distribution in the depth direction.
Tatsuya Naito
Filed: 24 May 20
Utility
Burst controller and burst control method of resonance converter
5 Oct 21
A switching period in a burst cycle includes three pulses, that is to say, a start pulse that turns on a low-side switching element, a main pulse that turns on a high-side switching element, and an end pulse that turns on the low-side switching element.
Koji Murata, Jian Chen
Filed: 31 Jan 20
Utility
Semiconductor device
28 Sep 21
A semiconductor device has first second-conductivity-type high-concentration regions, second second-conductivity-type high-concentration regions, third second-conductivity-type high-concentration regions, and fourth second-conductivity-type high-concentration regions.
Yasuyuki Hoshi
Filed: 31 Mar 20
Utility
Semiconductor integrated circuit
28 Sep 21
A semiconductor integrated circuit includes: a semiconductor monocrystalline region; an insulating film provided on a main surface of the semiconductor monocrystalline region; a conductive layer having a rectangular shape provided on the insulating film and including at least a polycrystalline layer of p-type; electric-field relaxing layers having a lower specific resistivity than the conductive layer and each including a polycrystalline layer of n-type so as to be arranged on both sides of the conductive layer in a direction perpendicular to a current-flowing direction; a high-potential-side electrode in ohmic contact with the conductive layer at one end of the conductive layer in the current-flowing direction; and a low-potential-side electrode in ohmic contact with the conductive layer and the respective electric-field relaxing layers at another end of the conductive layer opposed to the one end in the current-flowing direction, and having a lower potential than the high-potential-side electrode.
Hideaki Katakura
Filed: 25 Feb 20