3198 patents
Page 32 of 160
Utility
PEALD nitride films
11 Apr 23
A method of depositing nitride films is disclosed.
Hanhong Chen, Philip A. Kraus, Joseph AuBuchon
Filed: 18 Sep 20
Utility
Method of forming a 2-dimensional channel material, using ion implantation
11 Apr 23
A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting.
Keith T. Wong, Hurshvardhan Srivastava, Srinivas D. Nemani, Johannes M. van Meer, Rajesh Prasad
Filed: 15 Jan 21
Utility
4d11u3z931e34rsdlq9vfknzikmh5j4m2d1
11 Apr 23
Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide.
Raymond Hung, Mehul Naik, Michael Haverty
Filed: 30 Jul 21
Utility
ultp0am8huew4kagjtfsftxg21 p0kce4wwv7lbbcn9w8wnxn962vgbg
11 Apr 23
Exemplary substrate processing systems may include a chamber body defining a transfer region.
Viren Kalsekar
Filed: 23 Apr 20
Utility
3zzlac9d71opyleyb2gki i8ym6xs5gu4a0nj6efjc86qll
11 Apr 23
A robotic object handling system comprises a robot arm, a non-contact sensor, a first station, and a computing device.
Nicholas Michael Kopec, Damon K. Cox, Leon Volfovski
Filed: 25 Jun 19
Utility
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11 Apr 23
Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates.
Ludovic Godet, Wayne McMillan, Rutger Meyer Timmerman Thijssen, Naamah Argaman, Tapashree Roy, Sage Toko Garrett Doshay
Filed: 22 May 20
Utility
l04tq2gm3xr7wxlup43sr46rep9ux0beyp8ukl06kldpl2
11 Apr 23
Bit line stacks and methods of forming bit line stacks are described herein.
Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
Filed: 11 Jul 22
Utility
252mhgmi0s003uyzgxhvo qcyl34kpve70q2bj6xk7npekecv368
11 Apr 23
A method for forming a light emitting diode (LED) uses aluminum-based material layers and oxidation during the LED formation.
Shiva Rai
Filed: 6 Jan 21
Utility
2y06lh2wdupy365qhls9owxliglv3jnm3kdfidqafx1jf2bru
11 Apr 23
Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display.
Jungmin Lee, Yu Hsin Lin, Chung-Chia Chen, Ji Young Choung, Dieter Haas, Si Kyoung Kim
Filed: 3 Jun 22
Utility
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11 Apr 23
An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.
Gang Yu, Chung-Chia Chen, Wan-Yu Lin, Hyunsung Bang, Lisong Xu, Byung Sung Kwak, Robert Jan Visser
Filed: 19 Jan 21
Utility
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11 Apr 23
A power supply circuit includes a switchable match, including a high voltage bus connectable to a load, a low voltage bus connectable to the load such that the load is in series between the high voltage bus and the low voltage bus, at least two capacitors having a fixed value of capacitance selectively connectable between the high voltage bus and the low voltage bus and a plurality of solid state switches equal in number to the number of capacitors having a fixed value of capacitance connectable between the high voltage bus and the low voltage bus, each switch configured and arranged to selectively connect or disconnect one of the capacitors having a fixed value of capacitance selectively connectable between the high voltage bus and the low voltage bus into electrical communication between the high voltage bus and the low voltage bus, and a variable frequency power supply including a high voltage output connection, the high voltage connection connected to the high voltage bus.
Edward P. Hammond, IV, Yury Trachuk, Dmitry A. Dzilno
Filed: 5 Feb 21
Utility
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11 Apr 23
Substrate supports, substrate support assemblies and methods of using an arc generated between a first electrode and a second electrode to clean a support surface.
Tejas Ulavi, Arkaprava Dan, Sanjeev Baluja, Wei V. Tang
Filed: 24 Jan 22
Utility
7mwjkxvcooe10v4myu75fmzaevj3m6rpup0wq688uomvmt p3n89
11 Apr 23
A carrier head for chemical mechanical polishing includes a housing for attachment to a drive shaft, a membrane assembly beneath the housing with a space between the housing and the membrane assembly defining a pressurizable chamber, and a sensor in the housing configured to measure a distance from the sensor to the membrane assembly.
Steven M. Zungia, Jay Gurusamy
Filed: 6 Dec 19
Utility
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11 Apr 23
Embodiments of the present disclosure generally relate to chemical mechanical polishing (CMP) systems used in the manufacturing of semiconductor devices.
Andrew Nagengast, Steven M. Zuniga, Jay Gurusamy
Filed: 3 Nov 20
Utility
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11 Apr 23
According to one aspect of the present disclosure, a method of coating a substrate (100) with at least one cathode assembly (10) having a sputter target (20) and a magnet assembly (25) that is rotatable around a rotation axis (A) is provided.
Hyun Chan Park, Thomas Gebele, Ajay Sampath Bhoolokam
Filed: 2 Aug 21
Utility
ozlv6wn0p65og0gs8sguxwv41zdm2oge
11 Apr 23
An apparatus comprises a mounting panel including a top plate having multiple vias and multiple orifices.
Sohrab Zokaei, Kiran Garikipati, Shawn Thanhsan Le
Filed: 29 Apr 21
Utility
2t31f5te7zfyi5i bsnolr2zh3l4rquqv9zn
11 Apr 23
A fluorescent in-situ hybridization imaging and analysis system includes a flow cell to contain a sample to be exposed to fluorescent probes in a reagent, a fluorescence microscope to obtain sequentially collect a plurality of images of the sample at a plurality of different combinations of imaging parameters, and a data processing system.
Yun-Ching Chang, Dan Xie, Chloe Kim
Filed: 16 Dec 20
Utility
apdtcijoyhxomukq6gjcem3mqx9u0gurpcea85xxuw0g
4 Apr 23
A polishing article has a polishing surface and an aperture, the aperture including a first section and a second section.
Rajkumar Alagarsamy, Yongqi Hu, Simon Yavelberg, Periya Gopalan, Christopher R. Mahon
Filed: 6 Aug 20
Utility
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4 Apr 23
Embodiments of target assemblies for use in substrate processing chambers are provided herein.
Ilya Lavitsky, Keith A. Miller
Filed: 23 Oct 20
Utility
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4 Apr 23
Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber.
Yi Yang, Krishna Nittala, Karthik Janakiraman, Aykut Aydin, Diwakar Kedlaya
Filed: 2 Nov 20